The present invention relates to a fault detection system for an arithmetic unit and, more particularly, to fault detection system for multiplier used for both a normal multiplication and a division for calculating a quotient as a product of a dividend and an approximated reciprocal of a divisor.
As a conventional fault detection system for a multiplier, a modulo 3 check system is often used. This system has an actual multiplier, and a modulo 3 emulator to emulate the multiplier in modulo 3 arithmetic. For identical multipliers and multiplicands, the modulo 3 equivalent of the multiplication result by the actual multiplier and the multiplication result of the modulo 3 emulator are compared, thereby detecting a bit error.
The modulo 3 equivalent of binary data can be easily calculated by storing a simple known conversion in a memory such as a ROM as a program.
However, in order to apply the above modulo 3 fault detection system to a multiplier used for both normal multiplication and division for calculating a quotient as a product of a dividend and an approximated reciprocal of a divisor, special-purpose circuits for checking during normal multiplication and division must be provided to the actual multiplier and the modulo 3 emulator, resulting in a complicated circuit arrangement and an increase in the number of hardware components.